The present specification relates generally to bi-layer photoresists. In particular, the present specification relates to a bi-layer photoresist process.
Bi-layer photoresists and multilayer resists (MLR) have been utilized in photolithography. Typically, bi-layer resists are formed as follows. An organic layer is first spun onto a wafer containing underlayers. The organic layer typically has a thickness greater than the underlayers so that a smooth surface and substantially planar surface is provided. After pre-baking the organic layer, a thin imaging layer is deposited above the organic layer. High resolution patterns are created in the thin imaging layer using conventional photolithography techniques.
The higher resolution patterns are precisely transferred to the bottom organic layer using the imaging layer as a blanket exposure mask, or as an etching mask to pattern the organic layer. Patterns with resolutions less an 0.5 micrometers have been formed with such bi-layer resists. See, for example, R. Wolf, xe2x80x9cSilicon Processing for the VLSI Eraxe2x80x9d, Vol. 1, page 423.
Bi-layer and multilayer resists have been utilized to define various features including contacts or vias that electrically connect structures on an integrated circuit between interconnect layers (metal layers 1, 2, 3, 4 or 5). After defining the feature, the bi-layer or multilayer resist is stripped or removed from the substrate. Generally, the via extends between metal conductive lines between a conductive line and the semiconductor substrate (a silicide layer above the semiconductor substrate), between a polysilicon layer above the silicon substrate and a conductive or other structures.
According to one particular conventional lithographic process, conductive lines and vias are fabricated by a damascene process. In very and ultra-large scale integration (VLSI and ULSI) circuits, an insulating or dielectric material, such as silicon oxide, of the semiconductor device or IC is patterned in the damascene process with several thousand openings for the conductive lines and vias. The openings are filled with metal, such as aluminum or tungsten, and serve to interconnect the active and/or passive elements of the integrated circuit. The damascene process also is used for forming the multilevel signal lines of metal, such as copper, in the insulating layers, such as polyimide, of multilayer substrate on which semiconductor devices are mounted.
Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multilevel interconnection process in which, in addition to forming the grooves of single damascene, the conductive via openings also are formed. In the standard dual damascene process, the insulating layer is coated with a resist material which is exposed to a first mask with the image pattern of the via openings, and the pattern is anisotropically etched in the upper half of the insulating layer. After removal of the patterned resist material, the insulating layer is coated with a resist material which is exposed to a second mask with the image pattern of the conductive lines in alignment with the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched in the lower half of the insulating material. After the etching is complete, both the vias and grooves are filled with metal.
Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps. Although the standard dual damascene offers advantages over other processes for forming interconnections, it has a number of disadvantages, such as the edges of the via openings in the lower half of the insulating layer are poorly defined because of the two etchings and the via edges being unprotected during the second etching. Thus, improvements are needed in the standard dual damascene process to eliminate the poor edge definition of the via openings.
In addition, conventional dual damascene processes require that the dielectric layer be separately deposited before patterning begins. Further, conventional dual damascene processes require that at least two separate resist layers be completely stripped from the dielectric layer before conductive material is deposited.
Accordingly, there is a need for a bi-layer or multilayer resist process that can be utilized with a dual damascene technique. Further, there is a need of a dual damascene process utilizing a bi-layer or multilayer resist that can simultaneously form vias and conductive lines. Further still, there is a need for a simplified dual damascene process.
An exemplary embodiment relates to a method of forming dielectric material for conductive lines of an integrated circuit. The method includes forming a first lower, organic resist layer above a substrate, forming a first upper, silicon-containing resist layer above the first lower layer, patterning a first upper layer using a first etchant selective to the first upper layer with respect to the first lower layer to thereby form patterned first upper layer, and patterning the first lower layer using the patterned first upper layer as a hard mask and using a second etchant selective to the first lower layer with respect to the first upper layer. The first lower layer and the first upper layer correspond to a first layered resist. The method also includes a second lower, organic resist layer above the first upper, silicon-containing resist layer, forming a second upper, silicon-containing resist layer above the second lower layer, patterning the second upper layer using the first etchant selective to the second upper layer with respect to the second lower layer to thereby form a patterned second upper layer, and patterning the second lower layer using the patterned second upper layer as a hard mask using the second etchant selective to the second lower layer with respect to the second upper layer.
Another exemplary embodiment relates to a method of forming dielectric material for conductive lines of an integrated circuit. The method includes depositing a first layered photoresist above a substrate, the first layered photoresist including a first lower layer and a first upper layer, patterning the first upper layer using a first etchant selective to the first upper layer with respect to the first lower layer to thereby form a patterned first upper layer, and patterning the first lower layer using the patterned first upper layer as a hard mask and using a second etchant selective to the first lower layer with respect to the second upper layer. The method also includes depositing a second layered photoresist onto a substrate, the second layered photoresist including a second lower layer and a second upper layer, patterning the second upper layer using the first etchant selective to the second upper layer with respect to the second lower layer to thereby form a patterned second upper layer, and patterning the second lower layer using the patterned second upper layer as a hard mask and using a second etchant selective to the second lower layer with respect to the second upper layer.
Another exemplary embodiment relates to an integrated circuit. The integrated circuit includes an interconnect structure, the interconnect structure including a first surface and a second surface. The interconnect structure including a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is at least part of first layered photoresist and the second dielectric layer is at least part of a second layered photoresist.